In the consumer electronics industry, the mantra for innovation is higher device performance/less power. Arun Thathachary, a Ph.D. student in Penn State’s Electrical Engineering Department, spends his days and sometimes nights in the cleanroom of the Materials Research Institute’s Nanofabrication Laboratory trying to make innovative transistor devices out of materials other than the standard semiconductor silicon that will allow higher performance using less power.
Silicon has been the most successful material of the 20th century, with major global industries and even a valley named after it. But silicon may be running out of steam for high performance/low power electronics. For example, the compound semiconductor indium gallium arsenide is known to have far superior electron mobility than silicon. As silicon strains against the physical limits of performance, could a material like InGaAs provide enough of an improvement over silicon that it would be worth the expense in new equipment lines and training to make the switch worthwhile? Samsung, one of the world’s largest electronics companies, has funded Thathachary through his adviser, professor of electrical engineering Suman Datta, in a project to help them find out.
We developed a novel test structure called a Multi-fin Hall Bar Structure. It is the first such measurement of Hall mobility in a multi-fin 3D device," Thathachary said. "If you look at mainstream chip production today, all transistors are made in a 3D fashion, and because they are made in 3D rather than the earlier planar design, several mechanisms can degrade performance. What we looked at in that paper is how much degradation do you really suffer when going from a planar 2D surface to, in this case, 30 nm size features that are confined in 3D?
In an article in the journal Nano Letters early this year, Thathachary and his coauthors described a novel device prototype designed to test nanowires made of compound semiconductors such as InGaAs. Their goal was to see for the first time if such a compound material would retain its superior electron mobility at nanoscale dimensions in a so-called FinFET device configuration, the standard transistor architecture for sub-22 nanometer technology.