Saptarshi Das

Associate Professor Saptarshi Das

Research Interests

Ultra Low Power Electronics

Ever since the inception of metal oxide semiconductor field effect transistor (MOSFET), Scaling has been the primary driving force behind its unprecedented success. The early era of scaling (~1975-2005: Dennard Scaling) had two characteristic features: dimension scaling which allowed the number of transistor per chip to increase by 1000000x and consequently their speed to increase by 1000x, and voltage scaling which kept the power density practically constant throughout this scaling regime. However, around 2005, the voltage scaling almost stopped as further reduction in the supply voltage (VDD) and hence the threshold voltage (VTH) was leading to exponential increase in the OFF state current (IOFF). This is a direct consequence of non-scalability of the subthreshold swing (SS) to below 60mV/decade arising out of Boltzmann statistics that governs the operation of conventional MOSFETs. Dimension scaling, however, continued beyond 2005, but, under the new generalized scaling rules. This inevitably led to increase in the power density at the same rate as the integration density.  The actual scenario is made worse by non-scaling factors which escalated static and leakage power densities at a much faster rate. Power/heat dissipation, henceforth, became the main problem for high performance microprocessors. Today, in 2016, even dimension scaling seems extremely challenging beyond 10nm gate length (LG) owing to fundamental material limitations. So it is not too far when all aspects of MOSFET scaling will completely stop, marking the end of the silicon complementary metal oxide semiconductor (CMOS) era. Therefore, in order to restore the golden era of transistor scaling, energy efficient and high performance innovative device ideas based on aggressively scalable novel materials need to be conceived on an urgent and immediate basis.